DS3106LN+【PDF 2/92 页】IC TIMING LINE CARD 64-LQFP

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Sheet目录1994

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DS3106

6. Pin Descriptions

Table 6-1. Input Clock Pin Descriptions

PIN NAME

(1)

TYPE

(2)

PIN DESCRIPTION

REFCLK

Reference Clock. Connect to a 12.800MHz, high-accuracy, high-stability, low-noise local

oscillator (XO or TCXO). See Section 7.3.

IC3

IPD

Input Clock 3. CMOS/TTL. Programmable frequency. Default frequency selected by IPF[2:0]

pins when the

RST pin goes high, 8kHz if IPF[2:0] pins left open.

IC4

IPD

Input Clock 4. CMOS/TTL. Programmable frequency. Default frequency selected by IPF[2:0]

pins when the

RST pin goes high, 8kHz if IPF[2:0] pins left open.

Table 6-2. Output Clock Pin Descriptions

PIN NAME

(1)

TYPE

(2)

PIN DESCRIPTION

OC3

Output Clock 3. CMOS/TTL. Programmable frequency. Default frequency selected by

O3F[2:0] pins when the

RST pin goes high, 19.44MHz if O3F[2:0] pins left open. See Table

7-17.

OC6POS,

OC6NEG

ODIFF

Output Clock 6. LVDS/LVPECL. Programmable frequency. Default frequency selected by

O6F[2:0] pins when the

RST pin goes high, 38.88MHz if O6F[2:0] pins left open. The output

mode is selected by MCR8.OC6SF[1:0]. See Table 10-4, Table 10-5, Figure 10-1, and Figure

10-2.

FSYNC

8kHz FSYNC. CMOS/TTL. 8kHz frame sync or clock (default 50% duty cycle clock,

noninverted). The pulse polarity and width are selectable using FSCR1.8KINV and

FSCR1.8KPUL.

MFSYNC

2kHz MFSYNC. CMOS/TTL. 2kHz frame sync or clock (default 50% duty cycle clock,

noninverted). The pulse polarity and width are selectable using FSCR1.2KINV and

FSCR1.2KPUL.

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